Loading, Please Wait...
SAN JOSE, Calif., Oct. 17, 2019 (GLOBE NEWSWIRE) --
, the ProvenandTrustedchoice for Verification Intellectual Property (VIP) supporting simulation, emulation, field programmable gate array (FPGA) prototyping, post-silicon validation, formal property verification, Design IP, custom VIP and Design IP development, RISC-V verification services
WHAT: Will highlight its range of VIP at DVCon Europe (Booth #404) and demonstrate its Smart ViPDebug™, a protocol debugger that reduces debug time by rapidly identifying violations. It will profile its VIP support for Verilator, the free, open-source hardware description language (HDL) simulator. Also showcased will be TileLink VIP to verify the TileLink chip-scale interconnect standard, an open-source, high-performance and scalable cache-coherent fabric for RISC-V based system on chip (SoC) designs.
WHEN: Tuesday, October 29, and Wednesday, October 30
WHERE: Holiday Inn Munich City Centre, Munich, Germany
Attendees can schedule meetings to discuss SmartDV’s support for Verilator and TileLink or arrange for private demos at email@example.com to learn more about Smart ViPDebug.
is the Proven and Trusted choice for Verification and Design IP with the best customer service from more than 250 experienced ASIC and SoC design and verification engineers. Its high-quality standard or custom protocol Verification and Design IP are compatible with all verification languages, platforms and methodologies supporting all simulation, emulation, FPGA prototyping and formal verification tools used in a coverage-driven chip design verification flow. The result is Proven and Trusted Verification and Design IP used in hundreds of networking, storage, automotive, bus, MIPI and display chip projects throughout the global electronics industry. SmartDV is headquartered in Bangalore, India, with U.S. headquarters in San Jose, Calif. Visit SmartDV to learn more.
Connect with SmartDV at:
For more information, contact:
Public Relations for SmartDV