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CST: 19/09/2019 15:58:35   

eSilicon Tapes Out 7nm Combo PHY (HBM2/HBM2E/Low Latency) Test Chip

133 Days ago

Chip facilitates continued support of the latest HBM technologies for eSilicon’s 2.5D FinFET ASICs

SAN JOSE, Calif., May 09, 2019 (GLOBE NEWSWIRE) -- eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the tapeout of a 7nm test chip to provide silicon validation of its physical interface (PHY) to support the new JEDEC standard JESD235B, referred to informally as high bandwidth memory (HBM) 2E and emerging low-latency HBM technology.  The chip contains a 7nm PHY from eSilicon and a controller from Northwest Logic.  This 7nm test chip, along with a previously taped out 7nm test chip will be part of a 2.5D test system to verify end-to-end support for the new HBM interfaces. The PHY design is a “combo” device that supports HBM2, HBM2E and the emerging low-latency HBM interface in one physical IP block.

When compared to HBM2, the HBM2E standard increases total capacity from 8GB to 16GB, bandwidth per pin from 2.4 Gb/s to 3.2 Gb/s and bandwidth per stack from 307.2 GB/s to 410 GB/s. Samsung Electronics announced the industry’s first HBM2E to deliver the 3.2 Gb/s per-pin transfer speed, at NVIDIA’s GPU Technology Conference in March.

Low latency HBM devices have been launched by Renesas Electronics. These devices leverage Renesas low latency memory technology to realize high random-access rate and small data granularity as well as high bandwidth for latency-sensitive applications.

“We are pleased to work with our partner, eSilicon, on the validation of our Controller for HBM2E and low latency applications,” said Brian Daellenbach, president of Northwest Logic. “This validation further strengthens our industry-leading HBM2 Controller solution.”

“HBM memory stacks are a critical component for many of our new FinFET-class 2.5D ASICs,” said Hugh Durdan, vice president, strategy and products at eSilicon. “We look forward to validating the performance and functionality of our combo PHY and Northwest Logic’s controller to support the latest HBM capabilities.”

You can learn more about eSilicon’s 7nm IP platform here, or contact your eSilicon sales representative directly or via sales@esilicon.com. You can learn more about Northwest Logic’s HBM2 Controller Cores here.

About e Silicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com

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eSilicon is a registered trademark, and the eSilicon logo, neuASIC and “Collaborate. Differentiate. Win.” are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.

Contacts:  
Sally Slemons Nanette Collins
eSilicon Corporation Public Relations for eSilicon
sslemons@esilicon.com  nanette@nvc.com 

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